[Federal Register Volume 90, Number 30 (Friday, February 14, 2025)]
[Rules and Regulations]
[Pages 9604-9607]
From the Federal Register Online via the Government Publishing Office [www.gpo.gov]
[FR Doc No: 2025-02655]
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DEPARTMENT OF COMMERCE
Bureau of Industry and Security
15 CFR Part 774
[Docket No. 250207-0014]
RIN 0694-AJ98
Implementation of Additional Due Diligence Measures for Advanced
Computing Integrated Circuits; Amendments and Clarifications; and
Extension of Comment Period; Correction
AGENCY: Bureau of Industry and Security, Department of Commerce.
ACTION: Correcting amendment.
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SUMMARY: On January 16, 2025, BIS published in the Federal Register an
interim final rule (IFR), ``Implementation of Additional Due Diligence
Measures for Advanced Computing Integrated Circuits; Amendments and
Clarifications; and Extension of Comment Period'' (January 16 IFR).
This rule revises Export Control Classification Number (ECCN) 3A090 to
correct this ECCN's license requirement added in the January 16 IFR.
DATES:
Effective date: The effective date of this rule is
February 11, 2025.
Comment date: Comments on the correction in this rule must
be received by BIS no later than March 14, 2025.
ADDRESSES: Comments for the corrections in this rule may be submitted
to the Federal rulemaking
[[Page 9605]]
portal at: www.regulations.gov. The regulations.gov ID for this IFR is
BIS-2024-0055. Please refer to RIN 0694-AJ98 in all comments.
All filers using the portal should use the name of the person or
entity submitting the comments as the name of their files, in
accordance with the instructions below. Anyone submitting business
confidential information should clearly identify the business
confidential portion at the time of submission, file a statement
justifying nondisclosure and referring to the specific legal authority
claimed, and provide a non-confidential version of the submission.
For comments submitted electronically containing business
confidential information, the file name of the business confidential
version should begin with the characters ``BC.'' Any page containing
business confidential information must be clearly marked ``BUSINESS
CONFIDENTIAL'' on the top of that page. The corresponding non-
confidential version of those comments must be clearly marked
``PUBLIC.'' The file name of the non-confidential version should begin
with the character ``P.'' Any submissions with file names that do not
begin with either a ``BC'' or a ``P'' will be assumed to be public and
will be made publicly available at: https://www.regulations.gov.
Commenters submitting business confidential information are encouraged
to scan a hard copy of the non-confidential version to create an image
of the file, rather than submitting a digital copy with redactions
applied, to avoid inadvertent redaction errors which could enable the
public to read business confidential information.
FOR FURTHER INFORMATION CONTACT:
For general questions, contact Regulatory Policy Division,
Office of Exporter Services, Bureau of Industry and Security, U.S.
Department of Commerce at 202-482-2440 or by email: [email protected].
For Category 3 technical questions, contact Carlos Monroy
at 202-482-3246 or by email: [email protected].
SUPPLEMENTARY INFORMATION: On January 16, 2025, BIS published in the
Federal Register the IFR, ``Implementation of Additional Due Diligence
Measures for Advanced Computing Integrated Circuits; Amendments and
Clarifications; and Extension of Comment Period'' (90 FR 5298). This
correction amends ECCN 3A090 to correct the license requirement.
Correction to ECCN 3A090 License Requirement Table
This rule amends ECCN 3A090 by revising the first row and column in
the license requirements table. The first column of the first row of
the license requirements table is revised from ``RS applies to the
entire entry, except 3A090.a'' to read ``RS applies to 3A090.a''. The
regional stability section of the EAR already states the license
requirements for 3A090.a in Sec. 742.6(a)(6)(iii)(A). That provision
provides that there is a worldwide license requirement for ECCN 3A090.a
items. If Note 1 to 3A090.a does not apply, then the license
requirements for exports, reexports, or transfers (in-country) of ECCN
3A090.a items to destinations specified in Country Groups D:1, D:4, and
D:5 remain in effect with a compliance date of December 2, 2024,
consistent with the FDD IFR. Any items subject to Note 1 to ECCN
3A090.a are subject to worldwide license requirements with a compliance
date of January 31, 2025, consistent with the January 16 IFR.
Export Control Reform Act of 2018
On August 13, 2018, the President signed into law the John S.
McCain National Defense Authorization Act for Fiscal Year 2019, which
included ECRA (codified, as amended, at 50 U.S.C. 4801-4852). ECRA
provides the legal basis for BIS's principal authorities and serves as
the authority under which BIS issues this rule. In particular, and as
noted elsewhere, Section 1753 of ECRA (50 U.S.C. 4812) authorizes the
regulation of exports, reexports, and transfers (in-country) of items
subject to U.S. jurisdiction. Further, Section 1754(a)(1)-(16) of ECRA
(50 U.S.C. 4813(a)(1)-(16)) authorizes, inter alia, the establishment
of a list of controlled items; the prohibition of unauthorized exports,
reexports, and transfers (in-country); the requirement of licenses or
other authorizations for exports, reexports, and transfers (in-country)
of controlled items; apprising the public of changes in policy,
regulations, and procedures; and any other action necessary to carry
out ECRA that is not otherwise prohibited by law. Pursuant to Section
1762(a) of ECRA (50 U.S.C. 4821(a)), these changes can be imposed in a
final rule without prior notice and comment.
Rulemaking Requirements
1. Executive Orders 12866 and 13563 direct agencies to assess all
costs and benefits of available regulatory alternatives and, if
regulation is necessary, to select regulatory approaches that maximize
net benefits (including potential economic, environmental, public
health and safety effects and distributive impacts and equity).
Executive Order 13563 emphasizes the importance of quantifying both
costs and benefits and of reducing costs, harmonizing rules, and
promoting flexibility. Pursuant to Executive Order 12866, as amended,
this final rule has not been determined to be a ``significant
regulatory action.''
2. Notwithstanding any other provision of law, no person is
required to respond to, nor shall any person be subject to a penalty
for failure to comply with, a collection of information subject to the
requirements of the Paperwork Reduction Act of 1995 (PRA) (44 U.S.C.
3501 et seq.), unless that collection of information displays a
currently valid Office of Management and Budget (OMB) Control Number.
This rule involves the following OMB-approved collections of
information subject to the PRA:
0694-0088, ``Multi-Purpose Application,'' which carries a
burden hour estimate of 29.4 minutes for a manual or electronic
submission;
0694-0096, ``Five Year Records Retention Period,'' which
carries a burden hour estimate of less than 1 minute;
0694-0122, ``Licensing Responsibilities and Enforcement;''
which carries a burden hour estimate of 10 minutes per electronic
submission;
0694-0137, ``License Exceptions and Exclusions;'' which
carries a burden hour estimate of 5 minutes per electronic submission;
and
0607-0152, ``Automated Export System (AES) Program,''
which carries a burden hour estimate of 3 minutes per electronic
submission.
The January 16 IFR that this rule is correcting will affect the
collection under control number 0694-0088, for the multipurpose
application because of the increase of 375 more license applications.
BIS estimates that the changes included in the January 16 IFR will
result in a net increase of 375 multi-purpose applications (i.e., an
increase of 375 license applications) submitted annually to BIS.
However, the increase in burden falls within the existing burden
estimates currently associated with these control numbers.
The January 16 IFR that this rule is correcting also involves a
collection previously approved by the OMB under control number 0694-
0137, ``License Exceptions and Exclusions'' because this rule modifies
two EAR license exceptions, which now include new notification and
reporting requirements. Specifically, the January 16 IFR adds
[[Page 9606]]
two new types of requests that can be made under the existing advisory
opinion process and new reporting requirements. There are two types of
entities specified in Note 1 to 3A090.a that require submissions of
requests to be added, modified or removed as an approved IC designer or
approved ``OSAT'' company. These new reporting requirements related to
License Exceptions ACM and AIA are specified under Sec. Sec. 743.9 and
new Note 1 to 3A090.a of the EAR. These changes are expected to result
in an increase of 1,704 submissions related to this use of License
Exceptions AIA and ACM, submitted to BIS or to other parties involved
in the transaction. BIS estimates that these changes will result in an
increase in burden hours of 385 hours. This collection of information
fits within the scope of this information collection.
Additional information regarding these collections of information--
including all background materials--can be found at: https://www.reginfo.gov/public/do/PRAMain by using the search function to enter
either the title of the collection or the OMB Control Number.
3. This rule does not contain policies with federalism implications
as that term is defined in Executive Order 13132.
4. Pursuant to Section 1762 of ECRA (50 U.S.C. 4821), this action
is exempt from the Administrative Procedure Act (APA) (5 U.S.C. 553)
requirements for notice of proposed rulemaking, opportunity for public
participation, and delay in effective date. While Section 1762 of ECRA
on its own provides sufficient authority for such an exemption, this
action is also independently exempt from the same APA requirements
because it involves a military or foreign affairs function of the
United States (5 U.S.C. 553(a)(1)). Nonetheless, BIS is accepting
comments on this IFR.
5. Because a notice of proposed rulemaking and an opportunity for
public comment are not required to be given for this rule under the APA
(5 U.S.C. 553) or by any other law, the analytical requirements of the
Regulatory Flexibility Act (5 U.S.C. 601 et seq.) are not applicable.
Accordingly, no regulatory flexibility analysis is required, and none
has been prepared.
List of Subjects in 15 CFR Part 774
Exports, Reporting and recordkeeping requirements.
For the reasons stated in the preamble, part 774 of the Export
Administration Regulations (15 CFR parts 730 through 774) is corrected
as follows:
PART 774--THE COMMERCE CONTROL LIST
0
1. The authority citation for part 774 continues to read as follows:
Authority: 50 U.S.C. 4801-4852; 50 U.S.C. 4601 et seq.; 50
U.S.C. 1701 et seq.; 10 U.S.C. 8720; 10 U.S.C. 8730(e); 22 U.S.C.
287c, 22 U.S.C. 3201 et seq.; 22 U.S.C. 6004; 42 U.S.C. 2139a; 15
U.S.C. 1824; 50 U.S.C. 4305; 22 U.S.C. 7201 et seq.; 22 U.S.C. 7210;
E.O. 13026, 61 FR 58767, 3 CFR, 1996 Comp., p. 228; E.O. 13222, 66
FR 44025, 3 CFR, 2001 Comp., p. 783.
0
2. Supplement no. 1 to part 774 is amended by revising ECCN 3A090 to
read as follows:
Supplement No. 1 to Part 774--The Commerce Control List
* * * * *
3A090 Integrated circuits as follows (see List of Items Controlled).
License Requirements
Reason for Control: RS, AT
Country chart (see Supp. No.
Control(s) 1 to part 738)
RS applies to 3A090.a..................... To or within any destination
worldwide, see Sec.
742.6(a)(6)(iii)(A) of the
EAR.
RS applies to 3A090.b..................... To or within destinations
specified in Country Groups
D:1, D:4, and D:5 of
supplement no. 1 to part
740 of the EAR, excluding
any destination also
specified in Country Groups
A:5 or A:6. See Sec.
742.6(a)(6)(iii)(B) of the
EAR.
RS applies to 3A090.c..................... To or within Macau or a
destination specified in
Country Group D:5 of
supplement no. 1 to part
740 of the EAR. See Sec.
742.6(a)(6)(i)(B) of the
EAR.
AT applies to entire entry................ AT Column 1.
List Based License Exceptions (See Part 740 for a Description of All
License Exceptions)
LVS: N/A
GBS: N/A
NAC/ACA: Yes, for 3A090.a, if the item is not designed or marketed
for use in datacenters and has a 'total processing performance' of
4800 or more; yes, for 3A090.b, if the item is designed or marketed
for use in datacenters. N/A for 3A090.c.
HBM: Yes, for 3A090.c. See Sec. 740.25 of the EAR.
AIA: Yes, for 3A090.a.
ACM: Yes
LPP: Yes, for 3A090.a.
List of Items Controlled
Related Controls: (1) See ECCNs 3D001, 3E001, 5D002.z, and 5D992.z
for associated technology and software controls. (2) See ECCNs
3A001.z, 5A002.z, 5A004.z, and 5A992.z.
Related Definitions: N/A
Items:
a. Integrated circuits having one or more digital processing
units having either of the following:
a.1. A `total processing performance' of 4800 or more; or
a.2. A `total processing performance' of 1600 or more and a
`performance density' of 5.92 or more.
Note 1 to 3A090.a: When a ``front-end fabricator'' or ``OSAT''
company is seeking to export, reexport, or transfer (in-country) an
``applicable advanced logic integrated circuit,'' there is a
presumption that the item is 3A090.a and designed or marketed for
datacenters. If the ``front-end fabricator'' or ``OSAT'' company
cannot overcome this presumption, then it must comply with all
license requirements applicable to items specified in 3A090.a.
However, this presumption does not apply to any entity other than
the ``front-end fabricator'' or ``OSAT'' company. A ``front-end
fabricator'' or ``OSAT'' company can overcome this presumption in
any of the following three ways outlined in paragraphs a. through c.
of this Note 1.
a. If the designer of the ``applicable advanced logic integrated
circuit'' is an approved or authorized integrated circuit designer,
then a datasheet or other attestation of the `total processing
performance' and the `performance density' from the approved or
authorized integrated circuit designer indicating that the IC is not
specified in 3A090.a will overcome the presumption for the ``front-
end fabricator'' or ``OSAT'' company that the IC is specified in
ECCN 3A090.a.
(1) Approved integrated circuit designers are listed in
supplement no. 6 to this part of the EAR;
(2) Prior to April 13, 2026, authorized integrated circuit
designers include all integrated circuit designers:
(i) Headquartered in Taiwan or a destination specified in
Country Group A:1 or A:5, that are neither located in nor have an
ultimate parent headquartered in Macau or a destination specified in
Country Group D:5 of supplement no. 1 to part 740 of the EAR; and
(ii) That have agreed to submit applicable information described
in Sec. 743.9(b) to the ``front-end fabricator,'' which the
``front-end fabricator'' must then report to BIS.
(3) After April 13, 2026, authorized integrated circuit
designers include any integrated circuit designer that both meets
the criteria specified in subparagraph (2) and has submitted an
application to become an approved integrated circuit designer.
However, any company deemed an authorized IC designer after April
13, 2026, will cease to be an authorized IC designer 180 days after
the submission of its application to become an approved IC designer.
b. If the integrated circuit die is packaged by the ``front-end
fabricator'' at a location outside of Macau or a destination
specified in Country Group D:5 in supplement no. 1 to part 740, then
the attestation of the ``front-end fabricator'' that (a) the
``aggregated approximated transistor count'' of the final packaged
IC is below 30 billion transistors, or
[[Page 9607]]
(b) the final packaged IC does not contain high-bandwidth memory and
that the ``aggregated approximated transistor count'' of the final
packaged IC is below (i) 35 billion transistors for any exports,
reexports, or transfers (in-country) completed in 2027; or (ii) 40
billion transistors for any exports, reexports, or transfers (in-
country) completed in 2029 or thereafter, then this overcomes the
presumption by the ``front-end fabricator'' or ``OSAT'' company that
the IC is specified in ECCN 3A090.a.
c. If the integrated circuit is packaged by an approved ``OSAT''
company listed in supplement no. 7 to part 740 of the EAR, then the
attestation of the approved ``OSAT'' company that (a) the
``aggregated approximated transistor count'' of the final packaged
IC is below 30 billion transistors, or (b) the final packaged IC
does not contain high-bandwidth memory and that the ``aggregated
approximated transistor count'' of the final packaged IC is below
(i) 35 billion transistors for any exports, reexports, or transfers
(in-country) completed in 2027; or (ii) 40 billion transistors for
any exports, reexports, or transfers (in-country) completed in 2029
or thereafter, then this overcomes the presumption by the ``front-
end fabricator'' or ``OSAT'' company that the IC is specified in
ECCN 3A090.a.
d. It is not sufficient for the ``front-end fabricator'' or
``OSAT'' company to confirm the ECCN by relying on the attestation
of the end user or other party to the transaction, except under one
of the three ways enumerated in paragraphs a. through c. of this
note. In the absence of an attestation of the `total processing
performance' and the `performance density' by an approved integrated
circuit designer listed in supplement no. 6 to part 740 of the EAR,
the ``front-end fabricator'' or ``OSAT'' company must presume that
any logic integrated circuit produced using the ``16/14 nanometer
node'' or below, or using a non-planar transistor architecture and
destined for a commodity with an (a) ``aggregated approximated
transistor count'' of the final packaged IC is below 30 billion
transistors, or (b) the final packaged IC does not contain high-
bandwidth memory and that the ``aggregated approximated transistor
count'' of the final packaged IC is below (i) 35 billion transistors
for any exports, reexports, or transfers (in-country) completed in
2027; or (ii) 40 billion transistors for any exports, reexports, or
transfers (in-country) completed in 2029 or thereafter, or where the
``aggregated approximated transistor count,'' of the final, packaged
integrated circuit cannot be confirmed by the ``front-end
fabricator,'' or an approved ``OSAT'' company listed in supplement
no. 7 to part 740 of the EAR, is specified in ECCN 3A090.a and
designed or marketed for a datacenter.
Technical Note 1 to 3A090.a: The `approximated transistor count'
of a die is the `transistor density' of the die multiplied by the
area of the die measured in square millimeters. The `transistor
density' of the die is the number of transistors that can be
fabricated per square millimeter for the process node used to
manufacture the die. To calculate the number of `approximated
transistor count' of a die, a ``front end fabricator'' or ``OSAT''
company has two options. First, the ``front end fabricator'' or
``OSAT'' company may take the transistor density of the process node
used to manufacture the die and multiply this density by the area of
the die. This number may be significantly higher than the true
transistor count, but if the result is below the relevant transistor
threshold, then the ``front end fabricator'' or ``OSAT'' company can
be confident that the die in question will not exceed that
threshold. Second, to adjudicate edge cases, the ``front end
fabricator'' or ``OSAT'' company may use standard design
verification tools to estimate the number of (both active and
passive) transistors on the die using the GDS file.
b. Integrated circuits having one or more digital processing
units having either of the following:
b.1. A `total processing performance' of 2400 or more and less
than 4800 and a `performance density' of 1.6 or more and less than
5.92, or
b.2. A `total processing performance' of 1600 or more and a
`performance density' of 3.2 or more and less than 5.92.
Note 2 to 3A090.a and 3A090.b: 3A090.a and 3A090.b do not apply
to items that are not designed or marketed for use in datacenters
and do not have a `total processing performance' of 4800 or more.
For 3A090.a and 3A090.b items that are not designed or marketed for
use in datacenters and that have a `total processing performance' of
4800 or more, see license exceptions NAC and ACA.
Note 3 to 3A090.a and 3A090.b: Integrated circuits specified by
3A090 include graphical processing units (GPUs), tensor processing
units (TPUs), neural processors, in-memory processors, vision
processors, text processors, co-processors/accelerators, adaptive
processors, field-programmable logic devices (FPLDs), and
application-specific integrated circuits (ASICs). Examples of
integrated circuits are in the Note to 3A001.a.
Note 4 to 3A090.a and 3A090.b: For integrated circuits that are
excluded from ECCN 3A090 under Note 2 or 3 to 3A090, those ICs are
also not applicable for classifications made under ECCNs 3A001.z,
4A003.z, 4A004.z, 4A005.z, 4A090, 5A002.z, 5A004.z, 5A992.z,
5D002.z, or 5D992.z because those other CCL classifications are
based on the incorporation of an integrated circuit that meets the
control parameters under ECCN 3A090 or otherwise meets or exceeds
the control parameters or ECCNs 3A090 or 4A090. The performance
parameters under ECCN 3A090.c are not used for determining whether
an item is classified in a .z ECCN. See the Related Controls
paragraphs of ECCNs 3A001.z, 4A003.z, 4A004.z, 4A005.z, 4A090,
5A002.z, 5A004.z, 5A992.z, 5D002.z, or 5D992.z.
Technical Note 2 to 3A090.a and 3A090.b:
1. `Total processing performance' (`TPP') is 2 x `MacTOPS' x
`bit length of the operation', aggregated over all processing units
on the integrated circuit.
a. For purposes of 3A090, `MacTOPS' is the theoretical peak
number of Tera (1012) operations per second for multiply-accumulate
computation (D = A x B + C).
b. The 2 in the `TPP' formula is based on industry convention of
counting one multiply-accumulate computation, D = A x B + C, as 2
operations for purpose of datasheets. Therefore, 2 x MacTOPS may
correspond to the reported TOPS or FLOPS on a datasheet.
c. For purposes of 3A090, `bit length of the operation' for a
multiply-accumulate computation is the largest bit-length of the
inputs to the multiply operation.
d. Aggregate the TPPs for each processing unit on the integrated
circuit to arrive at a total. `TPP' = TPP1 + TPP2 + . . . . + TPPn
(where n is the number or processing units on the integrated
circuit).
2. The rate of `MacTOPS' is to be calculated at its maximum
value theoretically possible. The rate of `MacTOPS' is assumed to be
the highest value the manufacturer claims in annual or brochure for
the integrated circuit. For example, the `TPP' threshold of 4800 can
be met with 600 tera integer operations (or 2 x 300 `MacTOPS') at 8
bits or 300 tera FLOPS (or 2 x 150 `MacTOPS') at 16 bits. If the
integrated circuit is designed for MAC computation with multiple bit
lengths that achieve different `TPP' values, the highest `TPP' value
should be evaluated against parameters in 3A090.
3. For integrated circuits specified by 3A090 that provide
processing of both sparse and dense matrices, the `TPP' values are
the values for processing of dense matrices (e.g., without
sparsity).
4. `Performance density' is `TPP' divided by `applicable die
area'. For purposes of 3A090, `applicable die area' is measured in
millimeters squared and includes all die area of logic dies
manufactured with a process node that uses a non-planar transistor
architecture.
c. High bandwidth memory (HBM) having a `memory bandwidth
density' greater than 2 gigabytes per second per square millimeter.
Technical Note 1 to 3A090.c: `Memory bandwidth density' is the
memory bandwidth measured in gigabytes per second divided by the
area of the package or stack measured in square millimeters. In the
case where a stack is contained in a package, use the memory
bandwidth of the packaged device and the area of the package. High
bandwidth memory (HBM) includes dynamic random access memory
integrated circuits, regardless of whether they conform to the JEDEC
standards for high bandwidth memory (HBM), provided they have a
`memory bandwidth density' greater than 2 gigabytes per second per
square millimeter. This control does not cover co-packaged
integrated circuits with both HBM and logic integrated circuit where
the dominant function of the co-packaged integrated circuit is
processing. It does include HBM permanently affixed to a logic
integrated circuit designed as a control interface and incorporating
a physical layer (PHY) function.
* * * * *
Matthew S. Borman,
Principal Deputy Assistant Secretary for Strategic Trade and Technology
Security.
[FR Doc. 2025-02655 Filed 2-11-25; 4:15 pm]
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